plat: imx8m: Add caam module init on imx8m
authorJacky Bai <[email protected]>
Wed, 12 Jun 2019 09:41:47 +0000 (17:41 +0800)
committerJacky Bai <[email protected]>
Thu, 4 Jul 2019 11:59:43 +0000 (19:59 +0800)
CAAM module must be initialized in secure world
before it can be used in non-secure world.

Change-Id: I042893667ddef99d8b6fc3902847d516d8591996
Signed-off-by: Jacky Bai <[email protected]>
plat/imx/imx8m/imx8m_caam.c [new file with mode: 0644]
plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
plat/imx/imx8m/imx8mm/include/platform_def.h
plat/imx/imx8m/imx8mm/platform.mk
plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
plat/imx/imx8m/imx8mq/include/platform_def.h
plat/imx/imx8m/imx8mq/platform.mk
plat/imx/imx8m/include/imx8m_caam.h [new file with mode: 0644]

diff --git a/plat/imx/imx8m/imx8m_caam.c b/plat/imx/imx8m/imx8m_caam.c
new file mode 100644 (file)
index 0000000..478005e
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019, NXP. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+
+#include <imx8m_caam.h>
+
+void imx8m_caam_init(void)
+{
+       uint32_t sm_cmd;
+
+       /* Dealloc part 0 and 2 with current DID */
+       sm_cmd = (0 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART);
+       mmio_write_32(SM_CMD, sm_cmd);
+
+       sm_cmd = (2 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART);
+       mmio_write_32(SM_CMD, sm_cmd);
+
+       /* config CAAM JRaMID set MID to Cortex A */
+       mmio_write_32(CAAM_JR0MID, CAAM_NS_MID);
+       mmio_write_32(CAAM_JR1MID, CAAM_NS_MID);
+       mmio_write_32(CAAM_JR2MID, CAAM_NS_MID);
+
+       /* Alloc partition 0 writing SMPO and SMAGs */
+       mmio_write_32(SM_P0_PERM, 0xff);
+       mmio_write_32(SM_P0_SMAG2, 0xffffffff);
+       mmio_write_32(SM_P0_SMAG1, 0xffffffff);
+
+       /* Allocate page 0 and 1 to partition 0 with DID set */
+       sm_cmd = (0 << SMC_PAGE_SHIFT | 0 << SMC_PART_SHIFT |
+                       SMC_CMD_ALLOC_PAGE);
+       mmio_write_32(SM_CMD, sm_cmd);
+
+       sm_cmd = (1 << SMC_PAGE_SHIFT | 0 << SMC_PART_SHIFT |
+                       SMC_CMD_ALLOC_PAGE);
+       mmio_write_32(SM_CMD, sm_cmd);
+}
index 8bfb5452a748edba7882a217027cfd5a50bfa0ea..63d9223a2bd0255157bbace24c89f013ed255649 100644 (file)
@@ -24,6 +24,7 @@
 #include <gpc.h>
 #include <imx_aipstz.h>
 #include <imx_uart.h>
+#include <imx8m_caam.h>
 #include <plat_imx8.h>
 
 static const mmap_region_t imx_mmap[] = {
@@ -93,6 +94,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 
        imx_aipstz_init(aipstz);
 
+       imx8m_caam_init();
+
        console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
                IMX_CONSOLE_BAUDRATE, &console);
        /* This console is only used for boot stage */
index a95ab830352cee057c1bb4262be3be3da29f5f9e..de9e3b5c85a04542e2fb6bc3f81f0ae2be33cb48 100644 (file)
@@ -77,6 +77,7 @@
 #define IMX_NOC_BASE                   U(0x32700000)
 #define IMX_TZASC_BASE                 U(0x32F80000)
 #define IMX_IOMUX_GPR_BASE             U(0x30340000)
+#define IMX_CAAM_BASE                  U(0x30900000)
 #define IMX_DDRC_BASE                  U(0x3d400000)
 #define IMX_DDRPHY_BASE                        U(0x3c000000)
 #define IMX_DDR_IPS_BASE               U(0x3d000000)
index a3d249a65a274bef16bc6807861d0dd220736c1f..c28463b7c5fc845f0d68a533c888ed2b27858103 100644 (file)
@@ -20,6 +20,7 @@ IMX_GIC_SOURCES               :=      drivers/arm/gic/v3/gicv3_helpers.c      \
 BL31_SOURCES           +=      plat/imx/common/imx8_helpers.S                  \
                                plat/imx/imx8m/gpc_common.c                     \
                                plat/imx/imx8m/imx_aipstz.c                     \
+                               plat/imx/imx8m/imx8m_caam.c                     \
                                plat/imx/imx8m/imx8m_psci_common.c              \
                                plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c       \
                                plat/imx/imx8m/imx8mm/imx8mm_psci.c             \
index ce55d7f3134061f0581f824f284976c855010e80..26a3b364e93d4450ec58b067045956a8727f1d72 100644 (file)
@@ -24,6 +24,7 @@
 #include <gpc.h>
 #include <imx_aipstz.h>
 #include <imx_uart.h>
+#include <imx8m_caam.h>
 #include <plat_imx8.h>
 
 static const mmap_region_t imx_mmap[] = {
@@ -129,10 +130,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 
        imx_aipstz_init(aipstz);
 
-       /* config CAAM JRaMID set MID to Cortex A */
-       mmio_write_32(CAAM_JR0MID, CAAM_NS_MID);
-       mmio_write_32(CAAM_JR1MID, CAAM_NS_MID);
-       mmio_write_32(CAAM_JR2MID, CAAM_NS_MID);
+       imx8m_caam_init();
 
 #if DEBUG_CONSOLE
        static console_uart_t console;
index 959b820c52c1f05e91b41c863fac5d9de2b11f3b..3c212e37829b57cda4709201fed7097226e33c5b 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -70,6 +70,7 @@
 #define IMX_SNVS_BASE                  U(0x30370000)
 #define IMX_NOC_BASE                   U(0x32700000)
 #define IMX_TZASC_BASE                 U(0x32F80000)
+#define IMX_CAAM_BASE                  U(0x30900000)
 #define IMX_IOMUX_GPR_BASE             U(0x30340000)
 #define IMX_DDRC_BASE                  U(0x3d400000)
 #define IMX_DDRPHY_BASE                        U(0x3c000000)
 
 #define DEBUG_CONSOLE                  0
 #define IMX_WDOG_B_RESET
-
-#define CAAM_JR0MID                    U(0x30900010)
-#define CAAM_JR1MID                    U(0x30900018)
-#define CAAM_JR2MID                    U(0x30900020)
-#define CAAM_NS_MID                    U(0x1)
index d6879bf74ba5d5d1d7f3a47ef0a4db09c2d11857..44ce555871953d5406f4b1ec1287b21695f9ebeb 100644 (file)
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -22,6 +22,7 @@ BL31_SOURCES          +=      plat/imx/common/imx8_helpers.S                  \
                                plat/imx/imx8m/imx8mq/imx8mq_psci.c             \
                                plat/imx/imx8m/gpc_common.c                     \
                                plat/imx/imx8m/imx_aipstz.c                     \
+                               plat/imx/imx8m/imx8m_caam.c                     \
                                plat/imx/imx8m/imx8m_psci_common.c              \
                                plat/imx/imx8m/imx8mq/gpc.c                     \
                                plat/imx/common/imx8_topology.c                 \
diff --git a/plat/imx/imx8m/include/imx8m_caam.h b/plat/imx/imx8m/include/imx8m_caam.h
new file mode 100644 (file)
index 0000000..84725b1
--- /dev/null
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2019, NXP. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IMX8M_CAAM_H
+#define IMX8M_CAAM_H
+
+#include <lib/utils_def.h>
+
+#include <platform_def.h>
+
+#define CAAM_JR0MID            (IMX_CAAM_BASE + 0x10)
+#define CAAM_JR1MID            (IMX_CAAM_BASE + 0x18)
+#define CAAM_JR2MID            (IMX_CAAM_BASE + 0x20)
+#define CAAM_NS_MID            (0x1)
+
+#define JR0_BASE               (IMX_CAAM_BASE + 0x1000)
+
+#define SM_P0_PERM             (JR0_BASE + 0xa04)
+#define SM_P0_SMAG2            (JR0_BASE + 0xa08)
+#define SM_P0_SMAG1            (JR0_BASE + 0xa0c)
+#define SM_CMD                 (JR0_BASE + 0xbe4)
+
+/* secure memory command */
+#define SMC_PAGE_SHIFT         16
+#define SMC_PART_SHIFT         8
+
+#define SMC_CMD_ALLOC_PAGE     0x01    /* allocate page to this partition */
+#define SMC_CMD_DEALLOC_PART   0x03    /* deallocate partition */
+
+void imx8m_caam_init(void);
+
+#endif /* IMX8M_CAAM_H */